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? semiconductor component s industries, llc, 2017 1 publication order number : april 2017 - rev. 1 lc87f0k08a/d www.onsemi.com ordering information see detailed ordering and shipping info rmation on page 24 of this data sheet. * this product is licensed from s ilicon storage technology, inc. (usa). lc87f0k08a 8-bit microcontroller 8k-byte flash rom / 384-byte ram / 24-pin overview lc87f0k08a is an 8-bit microcomput er that, centered around a cpu running at a minimum bus cycle time of 83 .3 ns, integrates on a single chip a number of hardware features such as 8k-byte flash rom (onboard programmable), 384-byte ram, an on-chip debugger function, two sophisticated 16-bit timers/counters (may be divided into 8-bit timers), two 8-bit timers with a prescaler, a synchr onous sio interface, a uart port(full duplex), a 5-channel ad converter with 12/8-bit resolution selector, eight analog comparators, two amp circuits, ppg, a watchdog timer, an internal reset circuit, a system clock frequency divider, and a 21-source 10-vector interrupt feature. features ? flash rom ? capable of on-board programming with a power voltage range of 4.5 to 5.5 v ? block-erasable in 128 byte units ? writing in 2-byte units ? 8192 ? 8 bits ? ram ? 384 ? 9 bits ? package form ? dip24s, pb-free type ? minimum bus cycle time ? 83.3 ns (12 mhz) note: the bus cycle time here refers to the rom read speed. ? minimum instruction cycle time ? 250 ns (12 mhz) ? ports ? i/o ports ports whose i/o direction can be designated in 1 bit units : 9 (p00 to p07, p30) ? dedicated ppg output ports 1 (ppg0) ? dedicated amp/ cmp i/o ports 9 (cmp1ia, cmp1ib, cmp2i, cmp4i, cmp45i, cm5i, cmp6i, amp1i, amp2o) ? reset pin 1 (res#) ? dedicated on-chip debugger pin 1 (owp0) ? regulator output pin 1 (vdc) ? power pins 2 (vss1, vdd1) pdip24 / dip24s(300mil)
lc87f0k08a www.onsemi.com 2 ? timers ? timer 0 : 16-bit timer/counter with a capture register mode 0 : 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) ? 2 channels mode 1 : 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter (with an 8-bit capture register) mode 2 : 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register) mode 3 : 16-bit counter (with a 16-bit capture register) ? timer 1 : 16-bit timer/counter mode 0 : 8-bit timer with an 8-bit prescaler + 8-bit timer/counter with an 8-bit prescaler mode 2 : 16-bit timer/counter with an 8-bit prescaler mode 3 : 16-bit timer with an 8-bit prescaler ? timer 6 : 8-bit timer with a 6-bit prescaler (with toggle outputs) ? timer 7 : 8-bit timer with a 6-bit prescaler (with toggle outputs) ? base timer 1) the clock is selectable from the system clock and timer 0 prescaler output. 2) interrupts are programmable in 5 different time schemes ? serial interface ? sio1 : 8-bit synchronous serial interface mode 0 : synchronous 8-bit serial i/o (2-wire configuration, 2 to 512 tcyc transfer clocks) mode 2 : bus mode 1 (start bit, 8 data bits, 2 to 512 tcyc transfer clocks) mode 3 : bus mode 2 (start detect, 8 data bits, stop detect) ? uart ? full duplex ? 7 / 8 / 9 bit data bits selectable ? 1 stop bit (2 bits in continuous data transmission) ? built-in baudrate generator ? ad converter : 12 bits ? 5 channels ? 12 / 8-bit ad converter resolution selectable ? remote control receiver circuit (multiplexed with p07 / int3 / t0in pin) ? noise rejection function (noise filter time constant selectable from 1 tcyc / 32 tcyc / 128 tcyc) ? analog comparator : 8 channels ? cmp1 : "+" and "?" input pins output : for ppg output timing generation and capture timer input (int2) ? cmp2 : "+" input pin, "?" input is the internal vref (user select able options : 5/12, 6/12, or 7/12 vdd). output for interrupt flag setting (cmp2) ? cmp3 : "+" input is the output of amp1. "?" input is the internal vref (user select able options: 1/6, 2/6, 3/6, or 4/6 vdd). output for the ppg output control (only the existing cycle set to off), capture trigger of pulse on time and interrupt flag set (cmp3) ? cmp4 : "+" and "?" input pins output for the ppg output control (forced off) ? cmp5 : "?" input pin, "+" input is multiplexed with the "?" input pin of cmp4 output for the ppg output control (forced off) ? cmp6 : "+" input pin, "?" input is the internal vr ef (register setting: 1/6, 2/6, 3/6, or 4/6 vdd) output for the ppg output control (forced off) and interrupt flag set (cmp6) ? cmp7 : "+" input is multiplexed with the "+" input pin of cmp2 "?" input is the internal vref (user sel ectable options: 6/12, 7/12, or 8/12 vdd) output for the ppg output control (forced off) and interrupt flag set (cmp7). ? cmp8 : "+" input is multiplexed with the "+" input pin of cmp3 "?" input is the internal vref (register setting: 1/6, 2/6, 3/6, or 4/6 vdd) output for capture trigger of pulse on time and interrupt flag set (cmp8)
lc87f0k08a www.onsemi.com 3 ? amp circuit : 2 channels ? amp1 : the gain is set by user selectable options (6 / 8 / 10). input pin (amp1i) output is cmp3 input, cmp8 input and amp2 input. ? amp2 : the gain (1 / 2 / 4) is set by using a register. input is amp1 output. output pin (amp2o) ? igbt control circuit (ppg2) : 1 channel ? output sync signal switching : set by a register (1-pulse output / continuous pulse output synchronized with the cmp1 output) ? duty control : pulse start delay time and pulse on time with resp ect to a sync signal are set by using a register. ? ppg output control using cmp3 to cmp7 outputs ? surge detection using cmp4 / 5 / 6 outputs ? cmp1 output : pulse signal timing detection ? output polarity selectable : user selectable options ? clock output function capable of generating a clock output with a frequency of 1 1 , 2 1 , 4 1 , 8 1 , 16 1 , 32 1 , or 64 1 of the source oscillator clock selected as the system clock. ? watchdog timer ? can generate an internal reset signal on an overflow of timer that is running on the internal low-speed rc oscillation clock (30 khz). ? allows selection of continue, stop, or hold mode operation of the counter on entry into the halt/ hold mode. setting pulse start delay time
lc87f0k08a www.onsemi.com 4 ? interrupts ? 21 sources, 10 vector addresses 1) provides three levels (low (l), high (h), and highest (x)) of multiplex interrupt control. any interrupt request of the level equal to or lower than th e current interrupt is not accepted. 2) when interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. for interrupts of the same level, an interrupt into the smallest vector address is given priority. no. vector address level interrupt source 1 00003h x or l cmp2 / cmp7 2 0000bh x or l cmp3 / cmp8 3 00013h h or l int2 / t0l / int4 4 0001bh h or l int3 / base timer 5 00023h h or l t0h 6 0002bh h or l t1l / t1h 7 00033h h or l uart receive 8 0003bh h or l sio1 / uart transmit 9 00043h h or l adc / t6 / t7 / cmp1to 10 0004bh h or l cmp6 / surge detection ? priority levels x > h > l ? for interrupts of the same level, an interrupt with a smaller vector address is given priority. ? subroutine stack levels : up to 192 levels (the stack is allocated in ram.) ? internal high-speed multiplication/division instructions ? 16 bits ?? 8 bits ( 5 tcyc execution time) ? 24 bits ?? 16 bits (12 tcyc execution time) ? 16 bits 8 bits ( 8 tcyc execution time) ? 24 bits 16 bits (12 tcyc execution time) ? oscillation circuits ? internal oscillation circuits low-speed rc oscillation circuit : for system clock /watch dog timer (30 khz) medium-speed rc oscillation circuit : for system clock (1 mhz) high-speed rc oscillation circuit : for system clock /ppg clock (24 mhz) *the clock divided by two is used for system clock (12 mhz). ? system clock divider function ? can run on low current. ? the minimum instruction cycle selectable from 250 ns, 500 ns, 1 s, 2 s, 4 s, 8 s, 16 s, 32 s, and 64 s (at a main clock rate of 12 mhz). ? internal reset circuit ? power-on reset (por) function 1) por reset is generated only at power-on time. 2) the por release level can be selected from 5 levels (2.37 v, 2.57 v, 2.87 v, 3.86 v, and 4.35 v) by configuring options. ? low-voltage detection reset (lvd) function 1) lvd and por functions are combined to generate rese ts when power is turned on and when power voltage falls below a certain level. 2) the use/disuse of the lvd function and the low voltage threshold level (5 levels: 2.31 v, 2.51 v, 2.81 v, 3.79 v, 4.28 v) selectable by configuring options.
lc87f0k08a www.onsemi.com 5 ? standby function ? halt mode : halts instruction execution while allowing the peripheral circuits to continue operation. 1) oscillation is not halted automatically. 2) there are three ways of releasing the halt mode. (1) setting the reset pin to the low level (2) system resetting by watchdog timer or low-voltage detection (3) occurrence of an interrupt ? hold mode : suspends instruction execution an d the operation of the peripheral circuits. 1) the rc oscillators automatically stop operation. 2) there are three ways of releasing the hold mode. (1) setting the reset pin to the low level. (2) system resetting by watchdog timer or low-voltage detection (3) having an interrupt source esta blished at either int2 or int4. ? on-chip debugger ? supports software debugging with the ic mounted on the target board. ? data security function ? protects the program data stored in flash memory from unauthorized read or copy. note : this data security function does not necessarily provide absolute data security. ? development tools ? on-chip debugger: tcb87 type c + lc87f0k08a ? programming board package programming board dip24s w87f0kd ? flash rom programmer maker model supported version device on semiconductor single/gang programmer skk/skk type b (sanyofws) application version: 1.08 or later chip data version: 2.44 or later lc87f0k08 gang programmer skk-4g (sanyofws) note : be sure to check for the latest version.
lc87f0k08a www.onsemi.com 6 package dimensions unit : mm pdip24 / dip24s (300 mil) case 646aw issue a xxxxxxxxxx ymddd xxxxx = specific device code y = year m = month ddd = additional traceability data generic marking diagram* *this information is generic. please refer to device data sheet for actual part marking. to
lc87f0k08a www.onsemi.com 7 pin assignment dip24s name dip24s name 1 p30/buz/cmpxo 13 p02/an2 2 ppgo 14 cmp4i 3 res# 15 cmp45i 4 vss1 16 cmp5i 5 vdc 17 cmp6i 6 vdd1 18 amp2o 7 amp1i 19 p03/an3 8 cmp1ia 20 p04/an4/int4 9 cmp1ib 21 p05/si1/sb1/utx/clko 10 cmp2i 22 p06/sck11/urx/t6o 11 p00/an0 23 p07/int3/t0in/t7o/tppgo 12 p01/an1 24 owp0 top view pdip24/dip24s (300mil) ?pb-free type? owp0 p07/int3/t0in/t7o/tppgo p06/sck1/urx/t6o p05/si1/sb1/utx/clko p04/an4/int4 p03/an3 amp2o cmp6i cmp5i cmp45i cmp4i p02/an2 p30/buz/cmpxo ppgo res# vss1 vdc vdd1 amp1i cmp1ia cmp1ib cmp2i p00/an0 p01/an1 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13
lc87f0k08a www.onsemi.com 8 system block diagram interrupt control standby control ir pla flash rom pc bus interface port 0 ppg2 timer 0 timer 1 adc acc b register c register psw rar ram stack pointer alu timer 6 timer 7 uart1 sio1 on-chip debugger reset circuit (lvd/por) wdt reset control res# clock generator rc mrc src base timer int2 to 4 port 3
lc87f0k08a www.onsemi.com 9 pin function chart pin name i/o description option vss1 ? ? power supply pin no vdd1 ? ?? power supply pin no port 0 i/o ? 8-bit i/o port ? i/o specifiable in 1 bit units ? pull-up resistors can be turned on and off in 1 bit units. ? pin functions p04: int4 input / hold release input / timer 1 event input / timer 0l capture input / timer 0h capture input p05: sio1 data i/o / bus i-o / uart transmit / system clock output p06: sio1 clock i/o / uart receive / timer 6 toggle output p07: int3 input (with noise filter) / timer 0 event input timer 0h capture input / timer 7 toggle output / ppgo output (for monitor) p00(an0) to p04(an4): ad convertor input port interrupt acknowledge type rising falling rising & falling h level l level int3 int4 ? ? ? ? ? ? x x x x yes p00 to p07 port 3 i/o ? 1-bit i/o port ? i/o specifiable in 1 bit units ? pull-up resistors can be turned on and off in 1 bit units. ? pin functions p30: buzzer output / comparator output yes p30 amp1i i amp1 input pin no amp2o o amp2 output pin no cmp1ia i cmp1 ( ? ) input pin no cmp1ib i cmp1 (+) input pin no cmp2i i cmp2 (+) , cmp7 (+) input pin no cmp4i i cmp4 (+) input pin no cmp45i i cmp4 ( ? ), cmp5 (+) input pin no cmp5i i cmp5 ( ? ) input pin no cmp6i i cmp6(+) input pin no ppgo o ppg output port yes res# i/o external reset input / internal reset output pin no owp0 i/o debugger-dedicated pin no vdc o regulator output pin no port output types the table below lists the types of port outputs and the presence/absence of a pull-up resistor. data can be read into any input port even if it is in the output mode. port name option selected in units of option type output type pull-up resistor p00 to p07 1 bit 1 cmos programmable 2 n-channel open drain programmable p30 1 bit 1 cmos programmable 2 n-channel open drain programmable ppgo ? 1 cmos no 2 n-channel open drain no
lc87f0k08a www.onsemi.com 10 user option table option name option to be applied on flash-rom version option selected in units of option selection port output type p00 to p07 ? 1 bit cmos n-channel open drain p30 ? 1 bit cmos n-channel open drain ppgo ? ? cmos n-channel open drain ppgo output polarity ppgo ? 1 bit not inverted inverted amp gain amp1 ? 1 bit 6x 8x 10x cmp2vref ? ? ? 5/12vdd 6/12vdd 7/12vdd cmp3vref ? ? ? 1/6vdd 2/6vdd 3/6vdd 4/6vdd cmp7vref ? ? ? 6/12vdd 7/12vdd 8/12vdd ppg pulse on time ppg-pulse-on time upper limit ? ? 080h 100h 180h 200h 280h 300h 380h 400h 480h 500h 580h 600h 680h 700h 780h 7ffh low-voltage detection reset function detection function ? ? enabled: use disabled: disuse detection level ? ? 5-level power-on reset function power-on reset level ? ? 5-level
lc87f0k08a www.onsemi.com 11 recommended unused pin connections port name recommended unused pin connections board software p00 to p07 open output low p30 open output low amp1i, cmp1ai, cmp1ib, cmp2i, cmp4i, cmp45i cmp5i, cmp6i pull down with a 100 k ? resistor or less. ? amp2o open ? on-chip debugger pin connection requirements install and connect a limiting resistor (100 ? ) to the on-chip debugger dedicated pin (owp0) on the user board and pull the pin down (100 k ? ). it is recommended to install a dedicated connector to accept the cable to the debugging tool (tcb87 type c). th e connector must accommodate three lines, i.e., vss1, owp0, and vdd1. regulator output pin connection requirements the regulator output pin (vdc) must be connected a condenser (1 ? f) on the user's board. 100 k ? owp0 vss1 vdd1 100 ? connector for the debugging tool vdd gnd 1 ? f vdc vss1 this condenser is near vss1 terminal and vdc terminal
lc87f0k08a www.onsemi.com 12 1. absolute maximum ratings at ta = 25 ? c, vss1 = 0 v parameter symbol pin / remarks conditions specification vdd [v] min. typ. max. unit maximum supply voltage vddmax vdd1 ? 0.3 ? +6.5 v input voltage vi res#, amp1i, cmp1ia, cmp1ib, cmp2i, cmp4i, cmp45i, cmp5i, cmp6i ? 0.3 ? vdd+0.3 output voltage vo amp2o, ppgo ? 0.3 ? vdd+0.3 input/output voltage vio ports 0, 3 owp0 ? 0.3 ? vdd+0.3 high level output current peak output current ioph ports 0, 3, ppgo, owp0 cmos output select per 1 applicable pin ? 10 ma mean output current (note 1-1) iomh ports 0, 3, ppgo, owp0 cmos output select per 1 applicable pin ? 7.5 total output current ioah ports 0, 3, ppgo, owp0 total of all applicable pins ? 25 low level output current peak output current iopl (1) p02 to p07, ports 3, ppgo, owp0 per 1 applicable pin 20 iopl (2) p00, p01 per 1 applicable pin 30 mean output current (note 1-1) ioml (1) p02 to p07, ports 3, ppgo, owp0 per 1 applicable pin 15 ioml (2) p00, p01 per 1 applicable pin 20 total output current ioal (1) p00 to p03 total of all applicable pins 40 ioal (2) p04 to p07, ports 3, ppgo, owp0 total of all applicable pins 40 ioal (3) ports 0, 3,ppgo, owp0 total of all applicable pins 70 allowable power dissipation pdmax dip24s ta = ? 40 to +85 ? c mounted on thermal resistance test board (note 1-2) 460 mw operating ambient temperature topr ? 40 - +85 ? c storage ambient temperature tstg ? 55 - +125 note 1-1 : the mean output current is a mean value measured over 100 ms. note 1-2 : semi standards thermal resistance board (s ize: 76.1 114.3 1.6 t mm, glass epoxy) is used. stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should n ot be assumed, damage may occur and reliability may be affected.
lc87f0k08a www.onsemi.com 13 2. allowable operating conditions at ta = ? 40 to +85 ? c, vss1 = 0 v parameter symbol pin / remarks conditions specification vdd [v] min. typ. max. unit operating supply voltage vdd vdd1 0.242 s ? tcyc ? 200 s 4.5 5.5 v memory sustaining supply voltage vhd vdd1 ram and register contents sustained in hold mode. 2.0 high level input voltage vih (1) ports 0, 3, owp0 4.5 to 5.5 0.3vdd +0.7 vdd vih (2) res# 4.5 to 5.5 0.75vdd vdd low level input voltage vil (1) ports 3, owp0 4.5 to 5.5 vss 0.1vdd +0.4 vil (2) port 0 4.5 to 5.5 vss 0.15vdd +0.4 vil (3) res# 4.5 to 5.5 vss 0.25vdd instruction cycle time (note 2-1) tcyc (note 2-1) 4.5 to 5.5 0.242 200 s oscillation frequency range fmmrc internal high-speed rc oscillation. (note 2-2) 4.5 to 5.5 23.28 24.0 24.72 mhz fmrc internal medium-speed rc oscillation 4.5 to 5.5 0.5 1.0 2.0 fmsrc2 internal low-speed rc oscillation 4.5 to 5.5 15 30 60 khz note 2-1 : relationship between tcyc and os cillation frequency is 3/fmmrc at a divisi on ratio of 1/1 and 6/fmmrc at a division ratio of 1/2. note 2-2 : when switching the system clock, allow an oscillation stabilization time of 100 s or longer after the high-speed rc oscillator circuit transmits from the "oscillation stopped" to "oscillation enabled" state. the signal that divided high-speed rc oscillator clock by two is used for system clock (typ. 12 mhz). functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresses beyond the recomme nded operating ranges limits may affect device r eliab ility.
lc87f0k08a www.onsemi.com 14 3. electrical characteristics at ta = ? 40 to +85 ? c, vss1 = 0 v parameter symbol pin / remarks conditions specification vdd [v] min. typ. max. unit high level input current iih ports 0, 3, amp1i, cmp1ia, cmp1ib, cmp2i, cmp4i, cmp45i, cmp5i, cmp6i, res# output disabled pull-up resistor off vin = vdd (including output tr's off leakage current) 4.5 to 5.5 1 a low level input current iil ports 0, 3, amp1i, cmp1ia, cmp1ib, cmp2i, cmp4i, cmp45i, cmp5i, cmp6i, res# output disabled pull-up resistor off vin = vss (including output tr's off leakage current) 4.5 to 5.5 ? 1 amp allowable output current (note 3-1) iamp amp2o amp 1 gain is 8x and amp 2 gain is 1x selected amp1i = 0.445 v 5.0 ? 2.0 0.30 ma high level output voltage voh (1) ports 0 ioh = ? 1 ma 4.5 to 5.5 vdd ? 1 v voh (2) ports 3, ppgo, owp0 ioh = ? 6 ma 4.5 to 5.5 vdd ? 1 low level output voltage vol (1) p02 to p07, port 3, ppgo, owp0 iol = 10 ma 4.5 to 5.5 1.5 vol (2) p00, p01 iol = 25 ma 4.5 to 5.5 1.5 pull-up resistance rpu ports 0, 3 voh = 0.9vdd 4.5 to 5.5 15 35 80 k ? hysteresis voltage vhys ports 0,res#, owp0 p04 only when detecting int4 interrupt 4.5 to 5.5 0.1vdd v pin capacitance cp all pins for pins other than that under test: vin = vss f = 1 mhz, ta = 25 ? c 4.5 to 5.5 10 pf note 3-1 : product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product per formance may not be indicated by the electrical characteristics if operated under different conditions.
lc87f0k08a www.onsemi.com 15 4. serial i/o characteristics at ta = ? 40 to +85 ? c, vss1 = 0 v (note 4-1) parameter symbol pin / remarks conditions specification v dd [v] min. typ. max. unit serial clock input clock frequency tsck (1) sck1 (p06) ? see fig. 2. 4.5 to 5.5 2 tcyc low level pulse width tsckl (1) 1 high level pulse width tsckh (1) 1 output clock frequency tsck (2) sck1 (p06) ? cmos output selected ? see fig. 2. 4.5 to 5.5 2 low level pulse width tsckl (2) 1/2 tsck high level pulse width tsckh (2) 1/2 serial input data setup time tsdi sb1 (p05) ? must be specified with respect to rising edge of sioclk. ? see fig. 2. 4.5 to 5.5 (1/3)tcyc +0.01 s data hold time thdi 0.03 serial output output delay time tdd0 sb1 (p05) ? must be specified with respect to falling edge of sioclk. ? must be specified as the time to the beginning of output state change in open drain output mode. ? see fig. 2 4.5 to 5.5 (1/2)tcyc +0.05 note 4-1: these specifications are theoretical valu es. be sure to add marg in depending on its use. 5. pulse input conditions at ta = ? 40 to +85 ? c, vss1 = 0 v parameter symbol pin / remarks conditions specification v dd [v] min. typ. max. unit high/low level pulse width tpih (1) tpil (1) int3 (p07) when no noise filter is used, int4 (p04) ? interrupt source flag can be set. ? event inputs for timer 0 or 1 are enabled. 4.5 to 5.5 1 tcyc tpih (2) tpil (2) int3 (p07) when noise filter time constant is 1/1. ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 4.5 to 5.5 2 tpih (3) tpil (3) int3 (p07) when noise filter time constant is 1/32. ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 4.5 to 5.5 64 tpih (4) tpil (4) int3 (p07) when noise filter time constant is 1/128. ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 4.5 to 5.5 256 tpil (5) res# ? resetting is enabled. 4.5 to 5.5 200 s
lc87f0k08a www.onsemi.com 16 6. ad converter characteristics at vss1 = 0 v <12 bits ad converter mode at ta = ? 40 to +85 ? c > parameter symbol pin / remarks conditions specification vdd [v] min. typ. max. unit resolution n an0 (p00) to an4 (p04) 4.5 to 5.5 12 bit absolute accuracy et (note 6-1) 4.5 to 5.5 ? 16 lsb conversion time tcad see conversion time calculation formulas. (note 6-2) 4.5 to 5.5 32 115 s analog input voltage range vain 4.5 to 5.5 vss vdd v analog port input current iainh vain = vdd 4.5 to 5.5 1 a iainl vain = vss 4.5 to 5.5 ? 1 <8 bits ad converter mode at ta = ? 40 to +85 ? c > parameter symbol pin / remarks conditions specification v dd [v] min. typ. max. unit resolution n an0 (p00) to an4 (p04) 4.5 to 5.5 8 bit absolute accuracy et (note 6-1) 4.5 to 5.5 ? 1.5 lsb conversion time tcad see conversion time calculation formulas. (note 6-2) 4.5 to 5.5 20 90 s analog input voltage range vain 4.5 to 5.5 vss vdd v analog port input current iainh vain = vdd 4.5 to 5.5 1 a iainl vain = vss 4.5 to 5.5 ? 1 conversion time calculation formulas : 12 bits ad converter mode: tcad (conversion time) = ((52 / (ad division ratio)) + 2) (1/3) tcyc 8 bits ad converter mode: tcad (conversion time) = ((3 2 / (ad division ratio)) + 2) (1/3) tcyc internal oscillation (fmmrc) operating supply voltage range (vdd) system division ratio (sysdiv) cycle time (tcyc) ad division ratio (addiv) ad conversion time (tcad) 12-bit ad 8-bit ad 12 mhz 4.5 v to 5.5 v 1/1 250 ns 1/8 34.8 s 21.5 s note 6-1: the quantization error (1/2lsb) mu st be excluded from the absolute accuracy. the absolute accuracy must be measured in the microcontroller's state in which no i/o operations occur at the pins adjacent to the analog input channel. note 6-2: the conversion time refers to the period from the tim e an instruction for starting a conversion process till the time the conversion results register(s) are loaded with a complete di gital conversion value correspondi ng to the analog input value. the conversion time is 2 times the normal-time convers ion time when : ? the first ad conversion is performed in the 12- bit ad conversion mode af ter a system reset. ? the first ad conversion is performed after the ad conversi on mode is switched from 8-bit to 12-bit conversion mode.
lc87f0k08a www.onsemi.com 17 7. power-on reset (por) characteristics at ta = ? 40 to +85 ? c, vss1 = 0 v parameter symbol pin / remarks conditions specification option selected voltage min. typ. max. unit por release voltage porrl ? select from options. (note 7-1) 2.37 v 2.25 2.37 2.49 v 2.57 v 2.45 2.57 2.69 2.87 v 2.73 2.85 2.97 3.86 v 3.69 3.84 3.99 4.35 v 4.15 4.33 4.50 detection voltage unknown state pouks ? see fig. 4. (note 7-2) 0.7 0.95 power supply rise time poris ? power supply rise time from vdd = 0 v to 1.6 v. 100 ms note7-1 : the por release level can be selected out of 5 levels when the lvd reset function is disabled. note7-2 : por is in an unknown state before transistors start operation. 8. low voltage detection reset (lvd) characteristics at ta = ? 40 to +85 ? c, vss1 = 0 v parameter symbol pin / remarks conditions specification option selected voltage min. typ. max. unit lvd reset voltage (note 8-2) lvdet select from options. see fig. 5. (note 8-1) (note 8-3) 2.31 v 2.21 2.31 2.41 v 2.51 v 2.41 2.51 2.61 2.81 v 2.66 2.81 2.96 3.79 v 3.61 3.79 3.97 4.28 v 4.10 4.28 4.46 lvd detection voltage hysteresis lvhys 2.31 v 50 mv 2.51 v 50 2.81 v 50 3.79 v 50 4.28 v 50 detection voltage unknown state lvuks see fig. 5. (note 8-4) 0.7 0.95 v low voltage detection minimum width (reply sensitivity) tlvdw lvdet ? 0.5 v see fig. 6. 0.2 ms note8-1 : the lvd reset level can be selected out of 5 levels when the lvd reset function is enabled. note8-2 : lvd reset voltage specification va lues do not include hysteresis voltage. note8-3 : lvd reset voltage may exceed its specification values when port output state changes and/or when a large current flow s through port. note8-4 : lvd is in an unknown state before transistors start operation.
lc87f0k08a www.onsemi.com 18 9. amplifier and comparator characteristics at ta = ? 40 to +85 ? c, vss1 = 0 v parameter symbol pin / remarks conditions specification vdd [v] min. typ. max. unit common-mod e input voltage (note 9-1) vcmin cmp1ia,cmp1ib, cmp2i, cmp4i, cmp45i, cmp5i, cmp6i 4.5 to 5.5 vss vdd ? 1.5 v v internal reference voltage error vref cmp2, cmp3, cmp6, cmp7, cmp8 4.5 to 5.5 ? 0.02 +0.02 amp input voltage range (note 9-2) vamin amp1i 4.5 to 5.5 vss (vdd ? 1.5 v) / amp gain offset voltage voff(1) cmp1ia, cmp1ib (cmp1) cmp4i, cmp45i (cmp4) cmp45i, cmp5i (cmp5) ? within common-mode input voltage range 4.5 to 5.5 ? 20 mv voff(2) cmp2i (cmp2,cmp7), cmp6i (cmp6) ? within common-mode input voltage range ? including vref error 4.5 to 5.5 ? 40 voff(3) amp1i (cmp3,cmp8) ? within amp input voltage range ? amp1 gain set at 8x ? including amp1 output error and vref error 4.5 to 5.5 ? 28 amp output error vaer(1) amp2o ? amp1i = 0.41 v ? amp1 gain set at 8x ? amp2 gain set at 1x ? 155 ? 180 cmp1/cmp4/ cmp5 response time tc145rt ppgo, cmpxo(p30) ? within common-mode input voltage range ? input amplitude = 100 mv ? over drive = 50 mv 4.5 to 5.5 200 ns cmp3/cmp8 response time tc38rt ppgo, cmpxo(p30) ? amp1 gain set at 8x ? amp1i rising time ? mp1i = (vref 100 mv) / 8 ? see fig. 7. 4.5 to 5.5 600 cmp2 response time tc2rt cmpxo(p30) ? cmp input pin rising time ? cmp input = vref 50 mv 4.5 to 5.5 200 cmp6/cmp7 response time tc67rt ppgo, cmpxo(p30) ? cmp input pin rising time ? cmp input = vref 50 mv ? see fig. 7. 4.5 to 5.5 200 note 9-1 : when vdd = 5 v, the comparator in put voltage is effective from 0 to 3.5 v. note 9-2 : amp gain = amp1 gain amp2 gain when vdd = 5 v, amp1 gain = 8x, amp2 gain = 1x, th e amp input voltage is eff ective from 0 to 0.4375 v. note 9-3 : ppg output for cmp1 has a delay of 1/6 tcyc to 1/ 2 tcyc from cmpxo falling timing fo r synchronization with system clock, when the pulse start delay setup register is set to 000h.
lc87f0k08a www.onsemi.com 19 10. consumption current characteristics at ta = ? 40 to +85 ? c, vss1 = 0 v parameter symbol pin / remarks conditions specification vdd [v] min. typ. max. unit normal mode consumption current (note 10-1) (note 10-2) iddop(1) vdd1 ? system clock set to internal high speed rc oscillator ? internal low speed / medium speed rc oscillator stopped. ? 1/1 frequency division ratio 4.5 to 5.5 5.6 7.7 ma iddop(2) ? system clock set to internal medium speed rc oscillator ? internal low speed / high speed rc oscillator stopped. ? 1/2 frequency division ratio 4.5 to 5.5 1.8 2.9 iddop(3) ? system clock set to internal low speed rc oscillator ? internal medium speed / high speed rc oscillator stopped. ? 1/1 frequency division ratio 4.5 to 5.5 1.7 2.7 halt mode consumption current (note 10-1) (note 10-2) iddhalt(1) ? halt mode ? system clock set to internal high speed rc oscillator ? internal low speed / medium speed rc oscillator stopped. ? 1/1 frequency division ratio 4.5 to 5.5 3.5 4.9 iddhalt(2) ? halt mode ? system clock set to internal medium speed rc oscillator ? internal low speed / high speed rc oscillator stopped. ? 1/2 frequency division ratio 4.5 to 5.5 1.7 2.7 iddhalt(3) ? halt mode ? system clock set to internal low speed rc oscillator ? internal medium speed / high speed rc oscillator stopped. ? 1/1 frequency division ratio 4.5 to 5.5 1.6 2.7 hold mode consumption current (note 10-1) (note 10-2) (note 10-3) iddhold ? hold mode. ? when lvd option selected 4.5 to 5.5 1.6 2.7 note10-1 : values of the consumption current do not include current that flows into the output transistors and internal pull-up resistors. note10-2 : the consumption current valu es do not include operational current of lvd function if not specified. note10-3 : amp and cmp circuits are operating in hold mode.
lc87f0k08a www.onsemi.com 20 11. f-rom programming characteristics at ta = +10 to +55 ? c, vss1 = 0 v parameter symbol pin / remarks conditions specification vdd [v] min. typ. max. unit onboard programming current iddfw vdd1 ? excluding current consumption of the microcontroller block 4.5 to 5.5 7 11 ma programming time tfw (1) ? erasing operation 4.5 to 5.5 12 15 ms tfw (2) ? programming operation 35 45 s 12. uart (full duplex) operating conditions at ta = ? 40 to +85 ? c, vss1 = 0 v parameter symbol pin / remarks conditions specification vdd [v] min. typ. max. unit transfer rate ubr utx (p05) urx (p06) 4.5 to 5.5 16/3 8192/3 tcyc data length : 7 / 8 / 9 bits (lsb first) stop bits : 1 bit (2-bit in continuous data transmission) parity bits : none example of continuous 8-bit data transmission m ode processing (first transmit data = 55h) example of continuous 8-bit data reception mode processing (first receive data = 55h) transmit data (lsb first) start of transmission end of transmission ubr start bit stop bit receive data (lsb first) ubr start of reception end of reception stop bit start bit
lc87f0k08a www.onsemi.com 21 note : external circuits for reset may vary depending on the usage of por and lvd. please refer to the reset function in the user?s manual for more information. figure 1 sample reset circuit figure 2 serial i/o waveforms figure 3 pulse input timing signal waveform figure 4 example of waveforms observed when only por is used (lvd not used) (reset pin : pull-up resistor r res only) ? the por function generates a reset only when pow er is turned on starting at the vss level. ? no stable reset will be generated if power is turned on again when the power level does not go down to the vss level as shown in (a). if such a case is an ticipated, use the lvd functi on together with the por function or implement an external reset circuit. ? a reset is generated only when the power level goes down to the vss level as shown in (b) and power is turned on again after this condition continues for 100 s or longer. c res vdd r res res# tpil tpih di0 di7 di2 di3 di4 di5 di6 do0 do7 do2 do3 do4 do5 do6 di1 do1 sioclk: datain: dataout: dataout: datain: sioclk: tsc k tsckl tsckh thdi tsdi tddo
lc87f0k08a www.onsemi.com 22 figure 5 example of waveforms observed when both por and lvd functions are used (reset pin: pull-up resistor r res only) ? resets are generated both when power is turned on and when the power level lowers. ? a hysteresis width (lvhys) is provided to prevent th e repetitions of reset release and entry cycles near the detection level. v dd res# lvd hysteresis width (lvhys) reset unknown-state (lvuks) reset period reset period reset period lvd release voltage (lvdet+lvhys) lvd reset voltage (lvdet) v dd res# por release voltage (porrl) reset unknown-state (pouks) (a) (b) reset period reset period 100 s or longer
lc87f0k08a www.onsemi.com 23 figure 6 low voltage detection minimum width (example of momentary power loss / voltage variation waveform) figure 7 cmp response time vref + 50 mv vref vref ? 50 mv (vref + 100 mv) / 8 vref / 8 (vref ?? 100 mv) / 8 amp1i cmp6i/cmp7i ppgo tc38rt tc67rt v dd lvd detection voltage t lvdw v ss lvd release volta g e lvdet-0.5v
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